1. Technical Field
The present invention relates in general to integrated circuitry and in particular to an improved integrated circuit design that permits subcircuits within an integrated circuit to concurrently operate at different frequencies. Still more particularly, the present invention relates to an improved integrated circuit design that minimizes the effects of clock skew.
2. Description of the Related Art
At various stages in the historical development of integrated circuitry, integrated circuit designers have had to overcome different problems in order to reach higher performance benchmarks. Currently, large state-of-the-art integrated circuits such a microprocessors, which can include over 2 million transistors, can operate at clock frequencies of 300 MHz, 400 MHz and even higher. However, a number of problems must be overcome in order to be able to manufacture production quantities of large, complex integrated circuits capable of achieving clock speeds on the order of 1 GHz. One such problem is clock skew.
Clock skew results when clock signals are broadcast throughout a large semiconductor substrate. Because of propagation delays, the clock signals received by some portions of the integrated circuit may lag or lead those received by other portions of the integrated circuit. Clock skew is problematical since integrated circuits are typically designed so that all circuitry formed within a semiconductor substrate operates synchronously in response to the broadcast clock signals. Thus, when a signal is passed between two portions of the integrated circuit, the circuitry may fail to capture the signal or may erroneously detect the presence of a signal. While some clock skew is unavoidable and may not be detrimental to the proper operation of integrated circuits that operate at lower clock frequencies, clock skew becomes a critical design constraint as clock frequencies increase due to the decreased margin for timing errors. Moreover, efforts to reduce clock skew are exacerbated by the increasing size of integrated circuits. Thus, it is a challenge to develop a chip "floor plan" that permits signals to be transmitted between distant portions of the integrated circuitry without skew-induced errors.
A second related problem facing today's integrated circuit designers is the requirement that all integrated circuitry formed within a single semiconductor substrate operate at a common clock frequency. Because of the complexity of the logic, it is technically difficult for some portions of an integrated circuit design to be adapted to high frequency operation. Retaining the requirement that an entire integrated circuit operate at a single frequency can entail an unacceptably long development time and/or a large amount of additional logic to parallelize logical operations.
In order to overcome these obstacles to the realization of large, high-clock-speed (e.g., 1 GHz) integrated circuits, a new integrated circuit paradigm is required, which permits portions of the integrated circuit to operate independently at diverse frequencies and which minimizes the deleterious effects of clock skew.